This invention relates to an information processing unit which reduces the frequency of errors in an information processing unit which has an error detection function.
FIG. 6 shows, in a block diagram, a conventional information processing unit of this type, which includes an information processing device 1. The information processing device 1 is configured as a microcomputer which includes a central processing unit 1a, a program counter 1b, a ROM 1c, a RAM 1d, and an I/O port 1e. A portion of the memory area of an E.sup.2 PROM 2 is dedicated as a main memory device 2a which temporarily stores data words during the period between the stopping and the restarting of the operation of information processing device 1.
An error detection device 3 comprising four error detection circuits 3a, 3b, 3c, and 3d checks for errors during the reading of data words from main memory device 2a and generates an error signal if an error is detected. Specifically, as a data word is read, a combination of signal bits determined by the eight data lines comprising an I/O bus 20 (20a) are inputted to the error detection circuits 3a, 3b, 3c, and 3d. Error detection codes generated, based on the combination of these signal bits, are stored in the memory of the E.sup.2 PROM 2 (the signal line for this memory is not shown in FIG. 6). Thus, when a data word is read from the main memory unit 2a, the signal bits of the data word, combined as described above, are entered from the I/O bus 20 (20b). These error checking codes are used to determine whether or not there are errors in the word (a more detailed explanation is provided below). Moreover, if any of the error detection circuits 3a, 3b, 3c, or 3d detects an error, it outputs a "0" level error signal E.sub.1 -E.sub.4 respectively. FIG. 6, for the sake of simplicity, shows a separate input side 20a and an output side 20b for I/O bus 20. Time division multiplexing is actually used on the single bus 20.
If the error detection device 3 outputs an error signal, a correction device 4 corrects the data word read from the main memory unit 2a and passes it on to information processing device 1. The correction device 4 has 8 error correction circuits 4a, 4b, . . . , and 4h which correspond to each bit of the data word. Each of the error correction circuits 4a, 4b, . . . , 4h shown in FIG. 8 is a logic circuit comprised of a four input NAND gate 4x and a four input EX-NOR gate 4y. If an error occurs in a signal bit of a data word, each of the error correction circuits 4a-4h, controlled by the combination of output signals E.sub.1 -E.sub.4 from the four error detection circuits 3a-3d or of the inversion of these output signals by inverter 5, inverts the signal bit corresponding to the error.
FIG. 7 is a block diagram showing in greater detail the error detection device 3 of the information processing unit of FIG. 6. The input bus 20a combines five signal bits and enters them in the four error detection circuits 3a-3d respectively. An input side parity check circuit 3x performs a parity check on the five signal bits while an output side parity check circuit 3y performs a parity check on the same combination of five signal bits from the output bus 20b. An EX-NOR gate checks if the corresponding parity values obtained by parity check circuits 3x and 3y for the input side and the output side match.
A parity check memory unit 2b is allocated a memory area of the E.sup.2 PROM 2, at the same address as in the main memory device 2a, for reading and writing the parity values of the four bit units requested by the input side parity check circuit 3x. The parity check circuits 3x and 3y are composed, as shown in FIG. 9, of the four EX-NOR gates 3n. If the sum of the five one digit binary inputs Da-De entered in these parity check circuits is even, then a "0" is outputted; if the sum is odd, then a "1" is output.
Processing in conventional information processing units configured as described above is carried out in the following manner if an error occurs in a data word stored in the main memory device 2a.
The error detection circuits 3a-3d of the error detection device 3 are connected to the I/O bus 20 as shown in TABLE 1 (in TABLE 1, O means a connection and X means no connection). For example, while a data word is being written to the main memory device 2a, the five inputs Da-De of the parity checking circuit 3x on the input side of the error detection circuit 3a become the signal bits D1, D.sub.5, D.sub.6, D.sub.7 and D.sub.8. A parity value of "0" is output if the sum of the signal bits is even and a "1" if the sum of the signal bits is odd. The parity value is temporarily stored in the parity value memory unit 2b of the E.sup.2 PROM 2.
TABLE 1 ______________________________________ D.sub.1 D.sub.2 D.sub.3 D.sub.4 D.sub.5 D.sub.6 D.sub.7 D.sub.8 ______________________________________ 3a E.sub.1 O X X X O O O O 3b E.sub.2 O O O O X X X O 3c E.sub.3 O X O O X O O X 3d E.sub.4 O O X O O X O X ______________________________________
Similarly, the five inputs Da-De to the other error detection circuits 3b-3d become (D.sub.1, D.sub.2, D.sub.3, D.sub.4, D.sub.8), (D.sub.1, D.sub.3, D.sub.4, D.sub.6, D.sub.7), (D.sub.1, D.sub.2, D.sub.4, D.sub.5, D.sub.7). The parity values of these combinations of signal bits are stored temporarily in the corresponding areas D.sub.9 -D.sub.1 2 of the parity value memory unit 2b.
Next, while the central processor 12 reads a data word from a specified address in the main memory device 2a, the output side parity check circuit 3y of each of the error detection circuits 3a-3d requests the parity values for each of these same combinations of the five signal bits on the input side. The EX-NOR gate 3y checks if these parity values match the corresponding parity values stored in the parity value memory unit 2b.
If the parity values during read match the parity values during write, the error signals E.sub.1 -E.sub.4 which each of the EX-NOR gates 3z outputs become "1"s. If the parity values do not match, signals E.sub.1 -E.sub.4 become "0"s. The relationship between the correction of error signals E.sub.1 -E.sub.4 and each of the signal bits D.sub.1 -D.sub.8 can be shown by transposing the O mark with "0" and the X mark with "1" in TABLE 1 above. Accordingly, if E.sub.1 -E.sub.4 are all "0"s (error detection circuits 3a-3d have all detected errors), this shows that an error has occurred in signal bit D.sub.1. Taking another example, if E.sub.2 and E.sub.4 are both "0" and E.sub.1 and E.sub.3 are both "1", this shows that an error has occurred in signal bit D.sub. 2.
Each bit of a data word is entered into a corresponding error correction circuit 4a-4g in the correction device 4. Four inputs resulting from the combination of error signals E.sub.1 -E.sub.4 from the error detection circuits 3a-3d or the combination of inverted error signals E.sub.1 -E.sub.4, inverted by the inverter 5, are entered into a NAND gate 4x shown in FIG. 8. These four inputs control the corrections made on the signal bits entered in an EX-NOR gate 4y. For example, when signal bit D.sub.1 of a data word is entered in the correction circuit 4a, which serves an input on one side of the EX-NOR gate 4y, we can determine from TABLE 1 that the inverted signals E.sub.1 -E.sub.4 from error signals E.sub.1 -E.sub.4 are connected as the four inputs to the NAND gate 4x. If E.sub.1 -E.sub.4 are all "0"s, that is if an error has occurred in signal bit D.sub.1, the four inputs to the NAND gate 4x all become "1"s and its output becomes a "0". The EX-NOR gate 4y inverts bit signal D.sub.1 and then outputs the corrected signal bit. Similarly, the four inputs to the NAND gate 4x which serve as the correction circuit 4b for correcting signal bit D.sub.2 are, according to TABLE 1, E.sub.1, E.sub.2, and E.sub.4. If all four of these inputs are "1"s, that is when an error occurs in signal bit D.sub.2, EX-NOR gate 4y inverts signal bit D.sub.2 and outputs the corrected signal bit. The correction device 4 makes no corrections if there are no errors in the signal bits. The read data words are sent on to the information processing device 1 just as they were received.
However, while the information processing unit is completely stopped, data words which will be needed to restart processing are saved in the main memory unit 2a. These data words are read and used when the information processing unit is restarted. In this case, the data words stored in the main memory device 2a are read when the device restarts processing. The read data word is checked to determine if an error has occurred. There is a very high probability of errors occuring each time in a memory area containing an address while rewriting that address while a data word is written to the main memory device 2a during subsequent halts of the information processing unit.
Especially in a device such as E.sup.2 PROM, in which the presence or absence of a stored charge on an insulator produces a "1" or a "0" in a non-volatile memory serving as the main memory device 2a, if the power supply is cut while memory is stored in the device and the memory is not periodically refreshed as DRAMs are, then as more time since the data was written to memory memory errors become more frequent. In bad memory areas, after memory has been held for a long time, there is a high probability of having two or more bit errors in a single data word. The function for correcting a 1 bit error in a data word cannot correct these errors.